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GS8170DD36C-333/300/250/200 18mb 1x2lp cmos i/o double data rate sigmaram? 200 mhz?333 mhz 1.8 v v dd 1.8 v i/o 209-bump bga commercial temp industrial temp rev: 2.03 1/2005 1/29 ? 2002, gsi technology, inc. specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? double data rate read and write mode ? late write; pipelined read operation ? jedec-standard sigmaram ? pinout and package ? 1.8 v +150/?100 mv core power supply ? 1.8 v cmos interface ? zq controlled user-selectable output drive strength ? dual cycle deselect ? burst read and write option ? fully coherent read and write pipelines ? echo clock outputs track data output drivers ? 2 user-programmable chip enable inputs ? ieee 1149.1 jtag-complia nt serial boundary scan ? 209-bump, 14 mm x 22 mm, 1 mm bump pitch bga package ? pin-compatible with future 36mb, 72mb, and 144mb devices sigmaram family overview gs8170 dd 36 sigmarams are built in compliance with the sigmaram pinout standard for synchronous srams. they are 18,874,368-bit (18mb) srams. this family of wide, very low voltage cmos i/o srams is designed to operate at the speeds needed to implement economical high performance networking systems. rams are offered in a number of configurations including late write, double late write, and double data rate (ddr). the logical differences between the protocols employed by these rams mainly involve various approaches to write cueing and data transfer rates. the ram ? family standard allows a user to implement the interface protocol best suited to the task at hand. functional description because sigmarams are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. write cy cles are internally self-timed and initiated by the risi ng edge of the clock input. this feature eliminates complex off-chip write pulse generation required by asynchronous srams and simplifies input signal timing. in ddr mode the device captures data in on both rising and falling edges of clock and drives data on both clock edges as well. because the ddr ram always transfers data in two halves, a0 is internally set to 0 for the first half of each read or write transfer, and automatically incr emented to 1 for the falling edge transfer. the address field of a ddr ram is always one address pin less than the ad vertised index depth (e.g., the 512k x 36 has a 512k addressable index). rams support pipelined reads utilizing a rising-edge- triggered output register. ddr rams incorporate rising- and falling-edge-triggered output registers. they also utilize a dual cycle deselect (dcd) output deselect protocol. rams are implemented with high performance cmos technology and are packaged in a 209-bump bga. parameter synopsis key fast bin specs symbol - 333 cycle time tkhkh 3.0 ns access time tkhqv 1.8 ns
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 2/29 ? 2002, gsi technology, inc. 512k x 36 common i/o?top view (package c) 1234567891011 a nc nc a e2 a adv a e3 a dqb dqb b nc nc mcl nc a w a mcl nc dqb dqb c nc nc nc mcl nc (144m) e1 nc nc mcl dqb dqb d nc nc v ss nc nc mcl nc nc v ss dqb dqb e nc dqc v ddq v ddq v dd v dd v dd v ddq v ddq nc dqb f dqc dqc v ss v ss v ss zq v ss v ss v ss nc nc g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq nc nc h dqc dqc v ss v ss v ss ep3 v ss v ss v ss nc nc j dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq nc nc k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l nc nc v ddq v ddq v dd mcl v dd v ddq v ddq dqa dqa m nc nc v ss v ss v ss mch v ss v ss v ss dqa dqa n nc nc v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa p nc nc v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqd nc v ddq v ddq v dd v dd v dd v ddq v ddq dqa nc t dqd dqd v ss nc nc mcl nc nc v ss nc nc u dqd dqd nc a nc (72m) anc (36m) a ncncnc v dqd dqd a a a a1 a a a nc nc wdqddqdtmstdi a mcl atdotckncnc ? 2002.06 11 x 19 bump bga?14 x 22 mm 2 body?1 mm bump pitch ? note: users of cmos i/o sigmarams may wish to connect ?nc, v ref ? and the ?nc, ck ? pins to v ref (i.e., v ddq /2) to allow alternate use of future hstl i/o sigmarams.
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 3/29 ? 2002, gsi technology, inc. operation control all address, data and control inputs (with the exception of ep2, ep3, zq, and the mo de pins, l6, m6, and j6) are synchronized to rising clock edges. data in is captured on both rising and falling edges of ck. read and write operations must be initiated wit h the advance/load pin (adv) held low, in order to load the new address. device activation is accomplish ed by asserting all three of the chip enable inputs (e1 , e2, and e3). deasser tion of any one of the enable in puts will deactivate the device. it should be noted that only deactivation of the ram via e2 and/ or e3 deactivates the echo clocks, cq1?cq2. pin description table symbol description type comments a address input ? adv advance input active high w write enable input active low e1 chip enable input active low e2 & e3 chip enable input programmable active high or low ep2 & ep3 chip enable program pin mode input to be tied directly to v dd , v ddq or v ss ck clock input active high cq, cq echo clock output three state - deselect via e2 or e3 false dq data i/o input/output three state mch must connect high input active high to be tied directly to v dd or v ddq mcl must connect low input active low to be tied directly to v ss zq output impedance control mode input low = low impedance [high drive] high = high impedance [low drive] to be tied directly to v ddq or v ss tck test clock input active high tdi test data in input ? tdo test data out output ? tms test mode select input ? nc no connect ? not connected to die or any other pin v dd core power supply input 1.8 v nominal v ddq output driver power supply input 1.8 v nominal v ss ground input ?
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 4/29 ? 2002, gsi technology, inc. read operations double data rate read in applications where a data rate markedly faster than the ram? s latency is desired, the double data rate protocol doubles the data transfer rate (read or write bandwi dth) achieved in pipeline mode while keep ing the ram?s clock frequency constant. in double data rate mode, the ram multiplexes the results of a r ead out of the ram on half the usual number of data pins. the output register/mux behaves just as if it were in pipeline mode for the first transfer, but then makes a second transfer in res ponse to the next falling edge of clock as well. sigmaram ddr rams burst in linear order only. write operations write operation occurs when the following co nditions are satisfied at the rising edge of clock: all thr ee chip enables (e1 , e2, and e3) are active, the write enable input signal (w ) is asserted low, and adv is asserted low. double data rate write a double data rate write is a specialized form of late write. in double data rate mode, the ram will capture data in on both rising and falling edges of the ram clock, ck, beginning with the rising edge of clock that follows the capture of the write ad dress and command. double data rate pipelined read qa0 qa1 qc0 qc1 qd0 qd1 ck read deselect axx f read read read adv de c /e 1 /w dq address cq key hi-z access
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 5/29 ? 2002, gsi technology, inc. sigmaram double data rate read and write qa0 qa1 dc0 dc1 qd0 qd1 adv read cq e deselect cd write read read ck address a key hi-z access /e 1 /w dq f b
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 6/29 ? 2002, gsi technology, inc. special functions burst cycles srams provide an on-chip burst address generator that can be utili zed, if desired, to simplify bur st read or write implementati ons. the adv control pin, when driven high, commands the sram to advance the internal address counter and use the counter generated address to read or write the sram. the starting address for the first cycle in a burst cy cle series is loaded into th e sram by driving the adv pin low, into load mode. sigmaram ddr burst read with counter wrap-around counter wraps qa2 qa3 qa0 qa1 qa2 qa3 qb0 qb1 adv b3 a2 b0 cq dq /e 1 /w xx internal address a2 a0 b2 b1 a3 continue a1 a3 b1 b0 ck xx read continue external address a2 xx xx continue read
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 7/29 ? 2002, gsi technology, inc. sigmaram ddr burst write with counter wrap-around adv db2 cq da2 da3 da0 da1 da2 da3 db0 db1 /e 1 /w dq b2 b3 b1 counter wraps xx internal address a2 a3 a0 a1 a2 a3 b0 b1 xx b0 xx write continue continue write continue ck external address a2 xx
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 8/29 ? 2002, gsi technology, inc. burst order the burst address counter wraps around to its initial state after four internal addresses (the loaded address and three more) h ave been accessed. sigmarams always count in linear burst order. notes: 1. the burst counter wraps to initial state on the 3rd rising edge of clock. 2. the ddr sigmaram always begins an read or write at a0 = 0. a0 is internally set to 0 at the rising edge of clock and is not a vailable to the user. echo clock rams feature echo clocks, cq1, cq2, cq 1 , and cq2 that track the performance of the output drivers. the echo clocks are delayed copies of the main ram clock, ck. echo clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. the echo clocks are designed to fire with th e rest of the data output drivers. sigmarams provide both in-phase, or true, echo clock outputs (cq1 and cq2) and inverted echo clock outputs (cq1 and cq2 ). it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. programmable enables rams feature two user-programma ble chip enable inputs, e2 and e3. the sense of the inputs, whether they function as active low or active high inputs, is determined by the state of the prog ramming inputs, ep2 and ep3. for example, if ep2 is held at v dd , e2 functions as an active high enable. if ep2 is held to v ss , e2 functions as an active low chip enable input. programmability of e2 and e3 allows four banks of de pth expansion to be accomp lished with no additional logic. by programming the enable inputs of four srams in binary sequence (00, 01, 10 , 11) and driving the enable inputs with two address inputs, four srams can be made to look like one larger ram to the system. linear burst order a[1:0] 1st address (rising edge ck) 00 10 2nd address (falling edge ck) 01 11 3rd address (rising edge ck) 10 00 4th address (falling edge ck) 11 01
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 9/29 ? 2002, gsi technology, inc. example four bank dept h expansion schematic? 1x2lp a ck e1 e2 e3 w a 1 ?a n ck w dq 0 ?dq n bank 0 bank 1 bank 2 bank 3 bank enable truth table ep2 ep3 e2 e3 bank 0 v ss v ss active low active low bank 1 v ss v dd active low active high bank 2 v dd v ss active high active low bank 3 v dd v dd active high active high e1 a n ? 1 a n a 1 ?a n ? 2 a n ? 1 a n a 1 ?a n ? 2 a n ? 1 a n a 1 ?a n ? 2 a n ? 1 a n a 1 ?a n ? 2 dq a ck e2 e3 w dq a ck e2 e3 w dq a ck e2 e3 w dq e1 e1 e1 cq cq cq cq cq ep2 ep3 0 0 ep2 ep3 1 0 ep2 ep3 0 1 ep2 ep3 1 1
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 10/29 ? 2002, gsi technology, inc. it should be noted that deselection of the ram via e2 and e3 also deselects the echo clock output drivers. the deselection of echo clock drivers is always pipelined to the same degree as output data. deselection of the ram via e1 does not deactivate the echo clocks. in some applications it may be appropriate to pause between banks; to deselect both rams with e1 before resuming read operations. an e1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle in the bank. although the following drawing illustrates a e1 read pause upon switching from bank 1 to bank 2, a write to bank 2 would have the same effect, causing the ram in bank 2 to issue at least one cl ock before it is needed. echo clock control in two banks of double data rate sigmarams qa0 qa1 qc0 qc1 qb0 qb1 qd0 qd1 note: e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled f alse. cq1 + cq2 read read dq bank 2 cq bank 2 cq bank 1 read dq bank 1 address a b adv read read f /e2 bank 1 e2 bank 2 cde ck
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 11/29 ? 2002, gsi technology, inc. cmos output driver impedance control cmos i/o sigmarams are supplied wi th selectable (high or low) impedance output drivers. the zq pin allows selection between sram nominal drive strength (zq low) for multi-drop bus appl ications and low drive strength (zq high) point-to-point applications. sigmaram ddr bank switch with e1 deselect qa0 qa1 qc0 qc1 qd0 qd1 note: e1\ does not deselect the echo clock outputs. echo clock outputs are synchronously deselected by e2 or e3 being sampled f alse. f /e2 bank 1 e2 bank 2 dq bank 1 /e 1 c adv read d read dq bank 2 cq bank 1 cq1 + cq2 read cq bank 2 ck e read no op address a xx
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 12/29 ? 2002, gsi technology, inc. ddr late write, pipeli ned read truth table ck e1 (t n ) e (t n ) adv (t n ) w (t n ) previous operation current operation dq/cq (t n ) dq/cq (t n+? ) dq/cq (t n+1 ) dq/cq (t n+1? ) 0 1 x f 0 x x bank deselect ***/*** hi-z/hi-z 0 1 x x 1 x bank deselect bank deselect (continue) hi-z/hi-z hi-z/hi-z 0 1 1 t 0 x x deselect ***/*** hi-z/cq 0 1 x x 1 x deselect deselect (continue) hi-z/cq hi-z/cq 0 10 t 0 0 x write loads new address ***/*** d1/cq d2/cq 0 1x x 1 x write write continue increments address by 2 dn-2/cq dn-1/cq dn/cq dn+1/cq 0 10 t 0 1 x read loads new address ***/*** q1/cq q2/cq 0 1 x x 1 x read read continue increments address by 2 qn-2/cq qn-2/cq qn/cq qn+1/cq notes: 1. if e2 = ep2 and e3 = ep3 then e = ?t? else e = ?f?. 2. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?t rue?; ?f? = input ?false?. 3. ?***? indicates that the dq input requirement / output stat e and cq output state are determi ned by the previous operation. 4. dqs are tri-stated in response to bank deselect, deselect, and write commands, one full cycle after the command is sampled. 5. cqs are tri-stated in response to bank deselect co mmands only, one full cycle after the command is sampled. 6. one (1) continue operation may be initiated after a read or writ e operation is initiated to burst transfer a total of four (4 ) distinct pieces of data per single external address input. if a second (2nd) continue operation is initiat ed, the internal address wraps back to t he initial exter- nal (base) address.
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 13/29 ? 2002, gsi technology, inc. common i/o state diagram notes: 1. the notation ?x,x,x,x? controlling the state tr ansitions above indicate the states of inputs e1 , e, adv, and w respectively. 2. if (e2 = ep2 and e3 = ep3) then e = ?t? else e = ?f?. 3. ?1? = input ?high?; ?0? = input ?low?; ?x? = input ?don?t care?; ?t? = input ?true?; ?f? = input ?false?. deselect bank deselect read read write write continue x,f,0,x or x,x,1,x continue x,f,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x x,f,0,x 1,t,0,x 1,t,0,x or x,x,1,x 0,t,0,0 0,t,0,1 0,t,0,0 0,t,0,1 x,f,0,x x,f,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,0 0,t,0,1 1,t,0,x 0,t,0,0 0,t,0,1 x,x,1,x x,x,1,x 0,t,0,1 0,t,0,0 clock (ck) command current state next state ???? current state & next st ate definition for read /write control state diagram current state (n) next state (n + 1) transition ? input command code key n n+1 n+2 n+3
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 14/29 ? 2002, gsi technology, inc. note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the recommended operating conditions, for an extended period of time, ma y affect reliability of this component. recommended oper ating conditions absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.5 v v ddq voltage in v ddq pins ?0.5 to v dd v v i/o voltage on i/o pins ?0.5 to v ddq + 0.5 ( 2.5 v max.) v v in voltage on other input pins ?0.5 to v ddq + 0.5 ( 2.5 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 1.7 1.8 1.95 v 1.8 v i/o supply voltage v ddq 1.7 1.8 v dd v ambient temperature (commercial range versions) t a 02570 c1 ambient temperature (industrial range versions) t a ?40 25 85 c1 note: the part number of industrial temperature range versions end the character ?i?. unless otherwise noted, all performance specifi cations quoted are evaluated for worst case in the temperature range marked on the device. cmos i/o dc input characteristics parameter symbol min. typ. max. unit notes cmos input high voltage v ih 0.65 * v ddq ? v ddq + 0.3 v1 cmos input low voltage v il ?0.3 ? 0.35 * v ddq v1 note: for devices supplied with cmos input buffers. co mpatible with both 1.8 v and 1.5 v i/o drivers.
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 15/29 ? 2002, gsi technology, inc. note: this parameter is sample tested. ac test load diagram capacitance (t a = 25 o c, f = 1 mh z , v dd = 1.8 v) parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 45pf output capacitance c out v out = 0 v 67pf ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 20% tkc v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measurement and timing 20% tkc v dd + 1.0 v 50% v dd v il dq vt = v ddq /2 50 ? rq = 250 ? (hstl i/o)
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 16/29 ? 2002, gsi technology, inc. input and output leakage characteristics parameter symbol test co nditions min. max notes input leakage current (except mode pins) i il v in = 0 to v ddq ?2 ua 2 ua ? zq, mch, mcl, ep2, ep3 pin input current i inm v in = 0 to v ddq ?50 ua 50 ua ? output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua ? selectable impedance output dri ver dc electrical characteristics parameter symbol test co nditions min. max notes low drive output high voltage v ohl i ohl = ?4 ma v ddq ? 0.4 v ?1 low drive output low voltage v oll i oll = 4 ma ? 0.4 v 1 high drive output high voltage v ohh i ohh = ?8 ma v ddq ? 0.4 v ?2 high drive output low voltage v olh i olh = 8 ma ? 0.4 v 2 notes: 1. zq = 1; high impedance output driver setting 2. zq = 0; low impedance output driver setting operating currents parameter symbol -333 -300 -250 -200 test conditions 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current x36 i ddp (pl) 345 ma 355 ma 320 ma 330 ma 275 ma 285 ma 225 ma 235 ma e1 v il max. tkhkh tkhkh min. all other inputs v il v in v ih chip disable current x36 i sb1 (pl) 75 ma 85 ma 70 ma 80 ma 65 ma 75 ma 60 ma 70 ma e1 v ih min. or tkhkh tkhkh min. all other inputs v il v in v ih bank deselect current x36 i sb2 (pl) 75 ma 85 ma 70 ma 80 ma 65 ma 75 ma 60 ma 70 ma e2 or e3 false tkhkh tkhkh min. all other inputs v il v in v ih cmos deselect current i dd3 45 ma 55 ma 45 ma 55 ma 45 ma 55 ma 45 ma 55 ma device deselected all inputs v ss + 0.10 v v in v dd ? 0.10 v
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 17/29 ? 2002, gsi technology, inc. ac electrical characteristics parameter symbol -333 -300 -250 -200 unit notes min max min max min max min max clock cycle time tkhkh 3.0 ? 3.3 ? 4.0 ? 5.0 ? ns ? clock high time tkhkl 1.2 ? 1.3 ? 1.6 ? 1.8 ? ns ? clock low time tklkh 1.2 ? 1.3 ? 1.6 ? 1.8 ? ns ? clock high to echo clock low-z tkhcx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 2 clock high to echo clock high tkhch ? 1.8 1.8 ? 2.1 ? 2.1 ns ? clock low to echo clock low tklcl ? 1.8 1.8 ? 2.1 ? 2.1 ns clock high to echo clock high-z tkhcz ? 1.8 1.8 ? 2.1 ? 2.1 ns 1, 2 clock high to output low-z tkhqx1 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns 1 clock high to output valid tkhqv ? 1.8 1.8 ? 2.1 ? 2.1 ns ? clock low to output invalid tklqx 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns ? clock low to output valid tklqv ? 1.8 ? 1.8 ? 2.1 ? 2.1 ns ? clock high to output invalid tkhqx 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns ? clock high to output high-z tkhqz ? 1.8 1.8 ? 2.1 ? 2.1 ns 1 echo clock high to output valid tchqv ? 0.27 ? 0.29 ? 0.35 ? 0.35 ns 2 echo clock low to output invalid tclqx ?0.27 ? ?0.29 ? ?0.35 ? ?0.35 ? ns 2 echo clock low to output valid tclqv ? 0.27 ? 0.29 ? 0.35 ? 0.35 ns 2 echo clock high to output invalid tchqx -0.27 ? -0.29 ? -0.35 ? -0.35 ? ns 2 address valid to clock high tavkh 0.6 ? 0.7 ? 0.8 ? 0.8 ? ns ? clock high to address don?t care tkhax 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? enable valid to clock high tevkh 0.6 ? 0.7 ? 0.8 ? 0.8 ? ns ? clock high to enable don?t care tkhex 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? write valid to clock high twvkh 0.6 ? 0.7 ? 0.8 ? 0.8 ? ns ? clock high to write don?t care tkhwx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? data in valid to clock high tdvkh 0.32 ? 0.35 ? 0.40 ? 0.40 ? ns ? notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage tkhcz < tkhcx1.
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 18/29 ? 2002, gsi technology, inc. clock high to data in don?t care tkhdx 0.27 ? 0.30 ? 0.35 ? 0.35 ? ns ? data in valid to clock low tdvkl 0.32 ? 0.35 ? 0.40 ? 0.40 ? ns clock low to data in don?t care tkldx 0.27 ? 0.30 ? 0.35 ? 0.35 ? ns adv valid to clock high tadvvkh 0.6 ? 0.7 ? 0.8 ? 0.8 ? ns ? clock high to adv don?t care tkhadvx 0.4 ? 0.4 ? 0.5 ? 0.5 ? ns ? ac electrical character istics (continued) parameter symbol -333 -300 -250 -200 unit notes min max min max min max min max notes: 1. measured at 100 mv from steady state. not 100% tested. 2. guaranteed by design. not 100% tested. 3. for any specific temperature and voltage tkhcz < tkhcx1.
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 19/29 ? 2002, gsi technology, inc. timing parameter k ey?read cycle timing tkhqx tkhqz tkhqx1 tkhqv tavkh tkhax ck a dq (data out) tkhkh tklkh tkhkl cd e qb1 cq tchqv tclqv tclqx tkhch tkhcx1 tkhcz = cq high z tklqx tclch tchcl tchqx tklqv qb2
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 20/29 ? 2002, gsi technology, inc. timing parameter key?ddr c ontrol and data in timing jtag port operation overview the jtag port on this ram operates in a manner that is co mpliant with ieee standard 1149.1-1990, a serial boundary scan interfa ce standard (commonly referred to as jtag). the jtag port input interface levels scale with v dd . the jtag output drivers are powered by v ddq . disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain i nactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circ uits.to assure normal operation of the ra m with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. tkhnx tnvkh tavkh tkhax ck a ab c e1 , e2, e3, w , adv tkhdx tdvkh da1 da2 tkldx tdvkl ddr write dq (data in) note: tnvkh = tevkh, twvkh, etc. and tkhnx = tkhex, tkhwx, etc. db1 db2
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 21/29 ? 2002, gsi technology, inc. jtag port registers overview the various jtag registers, refered to as test access port ortap registers, are sele cted (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap registers is a serial shift register that captures seri al input data on the rising ed ge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed between the tdi and tdo pins . instruction register the instruction register holds the instructi ons that are executed by the tap controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. the instruction register can be loaded when it is placed between the tdi an d tdo pins. the instruction register is automat ically preloaded with the idcode instruction at power-up or when ever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and td o. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pins. the flip flops are then daisy chained together so the levels found can be shifted serially out of the jtag port?s tdo pin. the boundary scan regi ster also includes a number of place holder flip flops (always set to a logic 1). the relations hip between the device pins and the bits i n the boundary scan register is described in the sc an order table following. the boundary scan register , under the control of the tap controller, i s loaded with the contents of the rams i/o ring when the controller is in captur e-dr state and then is placed between the tdi and tdo pins when t he controller is moved to shift-dr state. sample-z, sample/preload and extest in structions can be used to acti vate the boundary scan register. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register pl aced between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state of the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap rese t) pin. trst is optional in ieee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up.
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 22/29 ? 2002, gsi technology, inc. jtag tap block diagram identification (id) register the id register is a 32-bit r egister that is loaded with a device and vendor s pecific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the code is loaded from a 32-bit on-chip rom. it describes various attri butes of the ram as indicated below. the register is then placed between the tdi and tdo pins when t he controller is moved into shift-dr sta te. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents die revision code not used i/o configuration gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 xxxx0000000000001000000110110011 instruction register id code register boundary scan register 0 1 2 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 23/29 ? 2002, gsi technology, inc. tap controller instruction set overview there are two classes of instructions defined in the standar d 1149.1-1990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on this device may be used to monitor all input and i/o pads, and can be used to load address, data or control si gnals into the ram or to preload the i/o buffers. when the tap controller is placed in capture-ir state the two l east significant bits of the in struction register are loaded wit h 01. when the controller is moved to the shift-ir state the instruction regi ster is placed between tdi and tdo. in this state the desired ins truction is serially loaded through the tdi input (while the previ ous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controll er is moved to update-ir state. the tap instru ction set for this device is listed in the fol lowing table. jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the boa rd level scan path to be shortened to facili- tate testing of other devices in the scan path. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 24/29 ? 2002, gsi technology, inc. sample/preload sample/preload is a standard 1149.1 mandatory public in struction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register may be loaded in parallel using the extest command. when the extest instruc- tion is selected, the sate of all the ram?s input and i/o pins, as well as the default values at scan register locations not as so- ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundary scan register location with which each output pin is associ- ated. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r future use. in this device they replicate the bypass instruction.
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 25/29 ? 2002, gsi technology, inc. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan register between tdi and tdo. 1 idcode 001 preloads id register and pl aces it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan register between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 111 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. notes: 1. include scope and jig capacitance. 2. test conditions as as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50 ? 30pf * jtag port ac test load * distributed test jig capacitance
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 26/29 ? 2002, gsi technology, inc. jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes 3.3 v test port input high voltage v ihj3 2.0 v dd3 +0.3 v1 3.3 v test port input low voltage v ilj3 ? 0.3 0.8 v 1 2.5 v test port input high voltage v ihj2 0.6 * v dd2 v dd2 +0.3 v1 2.5 v test port input low voltage v ilj2 ? 0.3 0.3 * v dd2 v1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 11ua4 test port output high voltage v ohj 1.7 ? v5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i ohjc = +100 ua
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 27/29 ? 2002, gsi technology, inc. jtag port timing diagram parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns tth tts ttkq tth tts tth tts ttkl ttkl ttkh ttkh ttkc ttkc tck tdi tms tdo parallel sram input
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 28/29 ? 2002, gsi technology, inc. 209 bga package drawing (package c) 14 mm x 22 mm body, 1.0 mm bump pitch, 11 x 19 bump array symbol min typ max units symbol min typ max units a ? ? 1.70 mm d1 ? 18.0 (bsc) ? mm a1 0.40 0.50 0.60 mm e 13.9 14.0 14.1 mm ? b 0.50 0.60 0.70 mm e1 ? 10.0 (bsc) ? mm c 0.31 0.36 0.38 mm e ? 1.00 (bsc) ? mm d 21.9 22.0 22.1 mm aaa ?0.15? mm rev 1.0 a a1 c ? b e e e e1 d1 d aaa bottom view side view
GS8170DD36C-333/300/250/200 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 2.03 1/2005 29/29 ? 2002, gsi technology, inc. ordering information?gsi sigmaram org part number type i/o speed (mhz) t a 512k x 36 GS8170DD36C-333 double data rate 1x 2 lp sram cmos 333 mhz c 512k x 36 gs8170dd36c-300 double data rate 1x 2 lp sram cmos 300 mhz c 512k x 36 gs8170dd36c-250 double data rate 1x 2 lp sram cmos 250 mhz c 512k x 36 gs8170dd36c-200 double data rate 1x 2 lp sram cmos 200 mhz c 512k x 36 GS8170DD36C-333i double data rate 1x 2 lp sram cmos 333 mhz i 512k x 36 gs8170dd36c-300i double data rate 1x 2 lp sram cmos 300 mhz i 512k x 36 gs8170dd36c-250i double data rate 1x 2 lp sram cmos 250 mhz i 512k x 36 gs8170dd36c-200i double data rate 1x 2 lp sram cmos 200 mhz i notes: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs817xx36c -300t. 2. t a = c = commercial temperature range. t a = i = industrial temperature range. ds/daterev. code: old; new types of changes format or content page;revisions;reason 8170dd18_r1 ? creation of new datasheet 8170dd18_r1; 8170dd18_r1_01 content ? removed all refe rences to ft mode 8170dd18_r1_01; 8170dd18_r2 content ? complete rewrite (dc from 36mb) 8170dd18_r2; 8170dd18_r2_01 content/format ? added 200 mhz speed bin ? updated format 8170dd18_r2_01; 8170dd18_r2_02 content/format ? pervasive edit ? added x72 information to ordering information 8170ddxx_r2_02; 8170ddxx_r2_03 content/format ? updated format ? removed preliminary banner due to qualification

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